Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. As used herein, “include” and “including” mean including without limitation.
One such FPGA is the Xilinx Virtex™ FPGA available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. Another type of PLD is the Complex Programmable Logic Device (“CPLD”). A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
For purposes of clarity, FPGAs are described below though other types of PLDs may be used. FPGAs may include one or more embedded microprocessors. For example, a microprocessor may be located in an area reserved for it, generally referred to as a “processor block.”
The ITU-T Video Coding Experts Group (“VCEG”) developed what is known as the H.264 specification, and the ISO/IEC Moving Picture Experts Groups (“MPEG”) developed what is known as the MPEG-4 Part 10 specification. These two specifications are maintained such that they have identical technical content under a collective partnership effort known as the Joint Video Team (“JVT”).
The H.264 specification proposes use of Variable Block Size (“VBS”) Motion Estimation (“ME”) and Mode Decision (“MD”). The use of VBS for ME and VBS for MD reduces Rate Distortion (“RD”) by allowing more active regions to be represented with more bits than less active regions. This enhancement in performance is in comparison with, for example, a fixed-size ME or fixed-size MD. However, VBS ME/MD heretofore has had a significant increase in H.264 encoder complexity. Because of the significant complexity associated with implementing VBS ME/MD in hardware, it made such hardware implementations impractical for many applications. In particular, the complexity associated with an encoder implemented in hardware for satisfying real-time constraints, in particular real-time high-definition encoding, was a significant limitation on use of VBS ME/MD.
To further complicate matters, the H.264 reference software, known as the Joint Model (“JM”) software, employs a brute force approach for implementing VBS ME/MD. For example, for VBS ME, all seven types of ME searches are performed, and an exhaustive search is performed to choose a best partitioning scheme among all possible combinations, namely among all possible MDs.
Accordingly, it would be desirable and useful to reduce the overall encoder complexity with minimal quality degradation for a wide range of bit rates.